The present invention relates to a row address strobe signal input buffer or "chain pre-charge" circuit of a highly integrated semiconductor device, more particularly, to such a buffer for preventing generation of a latch-up state by a floating status at the time of the power source voltage supply.
As the structure of semiconductor device became highly integrated, it became necessary to include various layers and patterns which are formed by using an elaborate fine manufacturing technique. Thus, the number of MOS transistors (or memory cells) inside a semiconductor device increased while the semiconductor chip size was considerably reduced.
When an initial power source voltage is supplied to a highly integrated semiconductor device which includes a plurality of MOS transistors, a large amount of current flows into each of MOS transistors for setting an initial value, and the substrate current becomes unstable. This causes problems of latch-up in each of the MOS transistors.
So-called latch-up state occurs when the MOS transistors formed in a semiconductor chip are triggered by an external noise, and hence a direct current flows from a power source voltage terminal to a ground terminal via each of the MOS transistors. This causes a serious disadvantage in that the MOS transistors of the semiconductor device are destroyed when a highly integrated semiconductor device is considered.
Therefore, it is necessary to form a circuit for protecting the chip at the time of initial power source voltage supply. Furthermore, when the initial power source voltage is in an unstable state, chain enable signals of the row address strobe signal RAS and the Column Address Strobe signal CAS, which are provided as machine cycles, are changed to a high level at the time of the power source voltage supply. Thus, the machine cycle is carried out, which causes an erroneous operation in the semiconductor device.
To resolve this problem, in the prior art, an initial start-up circuit has been built into the semiconductor device. By this, it is expected that the latch-up state at the time when an initial power source voltage is supplied be kept from occuring and that the semiconductor device be operated after the state of the DC power source voltage is maintained stable. This approach failed, however, to prevent a floating status of the chain generated during the power source voltage supply.
FIG. 1 is a diagram illustrating a conventional chain pre-charge circuit. The pad 1 is a node whereto a row address strobe signal RAS is input. The output side of the pad 1 is connected to a Schmitt trigger 2 which is able to produce the output of rectangular wave, and the output side of the Schmitt trigger 2 is connected to the gate circuit including inverters I1-I3 and a NAND gate.
In this circuit shown in FIG. 1, the pad 1 is in a floating state such that the pad can be changed into high level or low level at the beginning or during the initial power source voltage supply, hence there is some possibility that the chain enable signal .phi.R at the output terminal may be enabled in a high level state.
When the chain enable signal .phi.R is in a high level state as described above, RAS and CAS chain are operated and the latch-up state occurs. Signal .phi.1 is the chain feedback signal which acts as a writing signal generated at the time of the writing mode.
FIG. 2 is a circuit diagram of another conventional pre-charge circuit intended to resolve the problems in the circuit of FIG. 1. FIG. 2 shows a circuit construction for maintaining the chain enable signal .phi.R in a low level state at the time of power source voltage supply. More specifically, the circuit construction of FIG. 2 is basically the same as FIG. 1 except that the start-up signal .phi.2 of the start-up circuit is used for supplying stable power source voltage and clock signal at the time of the initial power source voltage supply.
In circuit of FIG. 2, the start-up signal .phi.2 is supplied to a gate of MOS transistor M1 which constitutes the Schmitt trigger 2. The MOS transistor M8 is connected between the Schmitt trigger 2 and the inverter I1, and the start-up signal .phi.2 is supplied to the gate of said MOS transistor M8. Furthermore, in the circuit of FIG. 2, one side of the NAND gate ND is connected to the power source voltage VCC or the signal .phi.1 generated at the time of the writing mode by switching means. The start-up signal .phi.2 is a pulse supplied from the start-up circuit, which is maintained in a high level state at the time of the power source voltage supply, and then allows the chain enable signal .phi.R be maintained in a low level state. When it elapses a predetermined time, after supplying the power source voltage VCC, said start-up signal .phi.2 transits from a high level to a low level. Thus, if the circuit of FIG. 2 is operated normally, the chain enable signal .phi.R becomes a high level or a low level value in accordance with the state of row address strobe signal RAS supplied to the pad 1.
The circuit shown in FIG. 2 has the following problems. First, the transition time of the start-up signal .phi.2 between a high level and a low level is highly variable according to the power-up rate or the value of power source voltage. Also, after the start-up signal .phi.2 has been changed to low level, there is some possibility of the chain enable signal .phi.R changing to high level in accordance with the floating status of a row address strobe signal RAS supplied to the pad 1.
Secondly, the possibility of the latch-up state is increased because the chain enable signal .phi.R changes more quickly from a high level state to a low level state as the power voltage VCC applied gets higher.